In a virtual memory system, the memory addresses used by a software program and the corresponding locations in the real memory are usually not the same. The portion of real memory, such as a random access memory (RAM), used by a program during an execution may not be identically addressed during subsequent executions. Because memory allocation is selected based on the memory space available in real physical memory, a software program will allocate portions of memory space based on its immediate processing needs.
Often, a virtual memory system allows a convenient mapping of virtual memory to that of real memory by way of partitioning memory into “pages” of various sizes. The mapping, or page translation, occurs by way of address translations using page table entries in one or more page tables that may be stored in one or more types of memory. For example, 4 kilobytes of virtual memory space may be mapped to 4 kilobytes of physical memory space. Since a control processor (i.e., central processing unit or CPU) requires quick access to the one or more page tables, these page table entries are implemented as close to the processor as possible, usually in the form of small page tables often referred to as translation lookaside buffers (TLBs). These TLBs contain the most recently used page translations. For example, a control processor's instruction fetch routines require a translation of virtual memory addresses to physical addresses; therefore, a translation lookaside buffer (TLB), is often implemented as one of the key components used by a control processor. The size of the “pages” that are accessed by the TLB may range from a few kilobytes to up to several megabytes in size. By accessing physical memory by way of the TLB, the physical memory location may be quickly determined when accessing data from memory. This facilitates the immediate access of data when a page hit occurs. Often, the TLB provides a translation of virtual addresses to physical memory addresses that is frequently used by the control processor. As a consequence, the CPU is able to process data more efficiently to improve overall performance of the computing system. Hence, the use of a TLB may have a significant role in implementing a virtual memory system.
Unfortunately, the methods used to access the page table entries in a TLB may not be very efficient. For example, the performance of the address translation may suffer based on how the TLB is addressed. Furthermore, the techniques currently used may require a TLB size that is larger than what may be required.
For example, a programmable TLB, as used in an exemplary MIPS architecture, is controlled by way of a set of control registers (e.g., TLB registers) and a set of instructions or commands. Furthermore, the page table entries are accessed using an addressing scheme that employs the use of odd and even pages (or page frames). Unfortunately, this scheme results in a less efficient way of accessing data required by the control processor (or CPU).
By performing address translation using both odd and even physical pages, the TLB size required for implementation may be unnecessarily large, resulting in increased fabrication costs of the manufacturer. This, of course, may have a significant effect on a manufacturer's costs.
Further limitations and disadvantages of conventional and traditional approaches will become apparent to one of skill in the art, through comparison of such systems with some aspects of the present invention as set forth in the remainder of the present application with reference to the drawings.